1. Field of the Invention
The present invention relates to a bus width control circuit and a cache memory comprising the same, which are used for enabling connection effectively and readily to various kinds of peripheral devices, in a data processor including an MPU (microprocessing unit) being connected to a system bus by means of a cache memory, for example, by enabling to use the system bus with a smaller data bus width than that of the MPU.
2. Description of the Related Art
In the data processor, access time from an MPU to a main memory tends to be shortened owing to both the improvement of the operational frequency of the MPU and various kinds of inventions. However, access time for a memory element which has high degree of integration mainly used for the main memory and the like is not so shortened, which becoming an obstacle in a tendency to allow the access operation from the MPU to the main memory to be executed at higher speed. In order to avoid such an obstacle, it is advantageous to employ a cache memory which consists of memory elements whose degree of integration is not so high but which are capable of being operated at high speed and are accessed in a shorter time. In other words, by holding a portion of the storage content of the main memory in the cache memory and supplying the content being stored in this cache memory into the MPU, the number of times for directly accessing the main memory is reduced, which enabling to substantially shorten the access time from the MPU to the main memory. This is used because a local access from the MPU to the main memory tends to be repeated many times.
FIG. 1 is a block diagram illustrating by way of example construction of a data processor wherein such a conventional cache memory as described above is installed.
In FIG. 1, reference numeral 21 designates an MPU and reference numeral 6 designates a system bus, and a cache memory 1 is provided between the both. The cache memory 1 is connected to the MPU 21 by means of an MPU bus 5. The system bus 6 is connected to various kinds of peripheral devices 41 . . . 4n including a main memory, and address spaces for the MPU 21 are allocated in the respective peripheral devices 41 . . . 4n.
Now will be described operation in read access by the MPU 21 in a specified address in the above described conventional construction of the data processor.
The read access by the MPU 21 is that the MPU 21 outputs an address being allocated in the peripheral devices 41 . . . 4n and reads the data being stored in the address of the peripheral device 41 . . . 4n. Tn the case where said data is not stored in the cache memory 1 yet (hereinafter referred to as cache miss) in the read access by the MPU 21, the cache memory 1 accesses to read said data for the peripheral devices 41 . . . 4n via the system bus 6 and fetches said data, inputting this to the MPU 21 via the MPU bus 5. In that case, in the case where the data being accessed to read is the data being in an address area subject to be cached (holding in cache memory), the cache memory 1 holds the data and its address therein.
On the other hand, in the case where said data is stored in the cache memory 1 (hereinafter referred to as cache hit) in the read access by the MPU 21, the cache memory 1 directly inputs its holding data corresponding to the address being outputted by the MPU 21 to the MPU 21 via the MPU bus 5. In that case, the cache memory 1 does not access to read said data for the peripheral devices 41 . . . 4n.
Next will be described operation in write access by the MPU 21 in a specified address.
The write access by the MPU 21 is that the MPU 21 outputs both an address being allocated in the peripheral devices 41 . . . 4n and the data to be stored in the address and then the MPU 21 writes the data in the address of the peripheral devices 41 . . . 4n. When the MPU 21 accesses to write data, the cache memory 1 outputs both said data and its address to the system bus 6 and accesses to write the data for the peripheral devices 41 . . . 4n. At the same time, in the case where the address of said data is held in the cache memory 1, the cache memory 1 updates its corresponding data.
Incidentally, in the above construction, there are cases where there is a problem of the bus widths of the MPU bus 5 and system bus 6. The MPU bus 5 is used for data transfer between the cache memory 1 and the MPU 21, and the system bits 6 is used for data transfer between the cache memory 1 and various kinds of peripheral devices, respectively.
Efficiency in the data transfer is improved by allowing the data bus width of the cache memory 1 being at a side of the MPU 21 to be coincident with the data bus width of the MPU 21, then, the width of the MPU bus 5 is arranged to be the same as the above bus width. And the width of the system bus 6 is the same as the data bus width of the cache memory 1 being at a side of the system bus 6. In the conventional cache memory 1, the bus width at the side of the system bus 6 is arranged to be the same as the bus width at the side of the MPU 21.
For example, in MC88200 manufactured by Motorola Company, both a P-bus being a data bus at the side of MPU 21 and an M-bus being a data bus at the side of the system bus 6 are arranged to be fixed at 32-bits width (See "MC88200 User's Manual").
As mentioned above, enlargement of the data bus width accompanied by the tendency to improve the performance of the MPU enlarges the width of the system bus. However, there are cases where it is not necessary to have not so wide bus width for such a peripheral device as the main memory.
FIG. 2 is a block diagram illustrating construction of a data processor comprising an MPU 21, a cache memory 1, a main memory 31 with the same bus width as that of the MPU 21, a submemory 34 with a different bus width from that of the MPU 21, and the like.
In the submemory 34, there is stored a program which needs not so much memory storage, such as an initial program loader (IPL). In such a small-storage memory as the submemory 34, there is not employed a method to have the width of N bits by arranging a plurality (N pieces, for example) pieces of memory element of 1-bit width (M bits in depth) as shown in FIG. 3, but there is generally employed a method to have a simple memory element which has its own bits-width to such a degree as shown in FIG. 4, i.e., N (.times.M) bits, for example.
As compared with the enlargement of the data bus width of the MPU 21, the data bus width of such a memory element as shown in FIG. 4 is not so enlarged, then, it becomes difficult to make the data bus width coincident with the bus width of the MPU 21. In that case, there is generated a need to provide such a bus width control circuit designated by reference numeral 14 in FIG. 2 between the submemory 34 and the system bus 6.
FIG. 5 is a block diagram illustrating a data processor comprising a shared memory 33 instead of the submemory 34 being provided in the above construction shown in FIG. 2, an MPU 22 with a different bus width from that of the MPU 21, a main memory 32 for this MPU 22, and a system bus 60 being connected to the MPU 22, main memory 32, and shared memory 33, in addition to those elements being comprised in the construction shown in FIG. 2.
The construction shown in FIG. 5 is an example for improving the capability of processing in the whole unit by further connecting the MPU 21 with an enlarged data bus width to an existing data processor.
In the construction shown in FIG. 5, the data bus widths of both the main memories 31, 32 are coincident with the respective data bus widths of the MPUs 21, 22. Then, in order to enable the access from the both MPUs 21, 22 to the shared memory 33, there is generated a need to provide the bus width control circuit 14 between the shared memory 33 and the system bus 6.
As mentioned above, in the conventional data processors shown in FIGS. 2 and 5, since the data bus width of the cache memory 1 being at a side of the system bus 6 is fixed to the data bus width of the MPU 21, there is a need to provide the bus width control circuit 14 to convert the data bus width. Specifically in the case where such a submemory 34 as shown in FIG. 2 is additionally provided in the construction shown in FIG. 5, there is generated another problem that it is necessary to provide the bus width control circuit 14 in both the shared memory 33 and in the submemory 34, respectively.